FORMAL VERIFICATION IN VERY LARGE-SCALE INTEGRATIONDESIGNING
Journal: BULLETIN OF KSAU
№ 4
, 2014
Rubrics: MATEMATIKA I INFORMATIKA
Authors:
1.
Sibirskiy federal'nyy universitet
2.
Sibirskiy federal'nyy universitet
3.
Sibirskiy federal'nyy universitet
4.
Sibirskiy federal'nyy universitet
Type:
Article
Pages:
from 87
to 89
Status:
Published
Received:
21.04.2014
Accepted:
23.04.2014
Published:
25.04.2014
Subject area:
004.052.42
Language:
Russian
Keywords:
verification, very large-scale integration (VLSI), functional programming, parallel computing
Abstract (English):
The main routes of the high-level synthesisof the VLSI gated descriptions are considered. The project verification problems on the functional level, inherent in traditional methods of design are defined. The basic provisions of the developed architecture-independent technology for VLSI representation on the basis of the functional-flow paradigm of parallel programming are presented. The approach to the project formal verification in the high level synthesis is offered.
The main routes of the high-level synthesisof the VLSI gated descriptions are considered. The project verification problems on the functional level, inherent in traditional methods of design are defined. The basic provisions of the developed architecture-independent technology for VLSI representation on the basis of the functional-flow paradigm of parallel programming are presented. The approach to the project formal verification in the high level synthesis is offered.
Keywords:
verification, very large-scale integration (VLSI), functional programming, parallel computing
verification, very large-scale integration (VLSI), functional programming, parallel computing
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2. Nemudroe V., Martin G. Sistemy-na-kristalle. Proektirovanie i razvitie. - M.: Tehnosfera, 2004.
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